Current leakage reduction for loaded bit-lines in on-chip memory structures

ABSTRACT

Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

[0001] This patent application claims the benefit of and is a divisionalof co-pending application Ser. No. 09/896,348, filed Jun. 28, 2001.

FIELD

[0002] Embodiments of the present invention relate to circuits, and moreparticularly, to memory circuits.

BACKGROUND

[0003] As semiconductor process technology provides for smaller andsmaller device size, sub-threshold leakage current in MOSFETs(Metal-Oxide-Semiconductor-Field-Effect-Transistor) may increase.Sub-threshold leakage current in a nMOSFET may occur when thegate-to-source voltage of the nMOSFET is less than its thresholdvoltage, V_(T). Sub-threshold leakage current may present designchallenges for various on-chip memory structures, such as, for example,register files, CAMs (Content-Addressable-Memory), caches, SRAM(Static-Random-Access-Memory), and DRAM (Dynamic-RAM).

[0004] Shown in FIG. 1 is a portion of an on-chip SRAM, or cache memory.For simplicity, only four cells are indicated. The content of the storeddata is read through complementary bit-lines 102 and 104 by senseamplifier 114. The cells are accessed by bringing one of word lines 106,108, 110, and 112 HIGH. In the particular embodiment of FIG. 1, wordline 106 is HIGH and word lines 108, 110, and 112 are LOW. By bringingword line 106, access nMOSFETs 116 and 118 are turned ON, and the stateof memory element 120 may be sensed by sense amplifier 114 via bit-lines102 and 104. The solid arrows nearby access nMOSFETs 116 and 118indicate that conduction current flows through access nMOSFETs 116 and118 to charge or discharge bit lines 102 and 104.

[0005] With word lines 108, 110, 112 LOW, access nMOSFETs 121 are OFFbecause their gate-to-source voltages are less than their thresholdvoltages. However, there may be sub-threshold leakage current, asindicated by the dashed arrows nearby nMOSFETs 121. In the particularembodiment of FIG. 1, assume that memory element 120 is such that node122 is HIGH, and memory elements 124 are such that nodes 126 are HIGH.Assume that bit-lines 102 and 104 are pre-charged to HIGH. When memorycell 120 is read, memory cell 120 will keep bit-line 102 HIGH and willbring bit-line 104 from HIGH to LOW. However, there will be contentionwith the sub-threshold leakage currents through access nMOSFETs 121,which try to charge bit-line 104 and discharge bit-line 102, oppositethe effect of the conduction current through access nMOSFETs 116 and118.

[0006] Shown in FIG. 2 is a portion of an on-chip register file. Thestate stored in memory element 202 is accessed by bringing read selectline 204 HIGH so that pass nMOSFET 206 is ON, and keeping the other readselect lines LOW. Assume that the state of memory element 202 is suchthat node 208 is LOW so that pass nMOSFET 210 is OFF. Assume that bitline 212 is pre-charged HIGH. Then, with read select line 204 broughtHIGH, bit-line 212 will not be discharged by conduction current.However, there may be sub-threshold leakage current through pass nMOSFET210 as indicated by the dashed arrow nearby nMOSFET 210. Assume alsothat nodes 214 are HIGH. Then, with read select lines 216 LOW, there maybe sub-threshold leakage current flowing through pass nMOSFETs 218.Consequently, the sub-threshold leakage currents depicted in FIG. 2 willtend to discharge bit-line 212, and may increase the noise margin.

[0007] As seen above, sub-threshold leakage current in memory structuresmay cause undesired voltage level changes in bit-lines, which may leadto incorrect read operations. One approach to mitigating this problem isto partition the bit-lines so as to reduce the number of memory cellsconnected to any one bit-line. However, this leads to an increase in thenumber of sense amplifiers, which increases die area and may reduceperformance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a prior art on-chip memory SRAM or cache.

[0009]FIG. 2 is a prior art on-chip register file.

[0010]FIG. 3 is an embodiment of the present invention for one memorycell of an on-chip SRAM or cache employing high-V_(T) accesstransistors.

[0011]FIG. 4 is an embodiment of the present invention for one memorycell of an on-chip register file employing high-V_(T) pass transistors.

[0012]FIG. 5 is another embodiment of the present invention for onememory cell of an on-chip SRAM or cache employing a negative word linevoltage for a no-read operation.

[0013]FIG. 6 illustrates the word line voltage of the embodiment of FIG.5 during a transition from a read operation to a no-read operation.

[0014]FIG. 7 is an embodiment of the present invention for one memorycell of an on-chip register file employing a negative word line voltagefor a no-read operation.

[0015]FIG. 8 is an embodiment of the present invention for one memorycell of an on-chip SRAM or cache employing access transistors in astacked configuration.

[0016]FIG. 9 is an embodiment of the present invention for one memorycell of an on-chip register file employing pass transistors in a stackedconfiguration.

DESCRIPTION OF EMBODIMENTS

[0017] A portion of a memory structure, such as an on-chip SRAM orcache, is shown in FIG. 3, where for simplicity one memory cell 302 andone word line 304 are explicitly illustrated. Also shown in FIG. 3 isdriver 306 for driving word line 304. Access nMOSFETs 308 are high-V_(T)(high threshold voltage) nMOSFETs. That is, the threshold voltage foraccess nMOSFETs 308 is higher than the threshold voltage of other, lowerthreshold voltage transistors in the memory circuit, such as transistorsin memory cell 302, and lower than the supply voltage V_(cc). In someembodiments, the threshold voltage for access nMOSFETs 308 may be 80 mVto 300 mV higher than the other, lower threshold voltage transistors.Or, the threshold voltage for nMOSFETs 308 may be such that its leakagecurrent is substantially less, e.g., ten to one hundred times less, thanleakage current in other, lower threshold voltage transistors, such astransistors in memory cell 302.

[0018] It is found that using high-V_(T) access nMOSFETs reducessub-threshold leakage current. However, high-V_(T) nMOSFETs have lowergain than nMOSFETs with lower threshold voltages. It has generally beenbelieved that scaling up various device features to compensate for lowergain devices would not help to increase the overall circuit performance.However, the authors of these letters patent have found that thetopology of memory structures is such that high threshold voltagenMOSFETs may be scaled larger in order to achieve higher performance,and the scaling up of pass or access nMOSFETs does not necessarilyaffect the performance of read operations. Scaling up the pass or accessnMOSFETs increases their gate capacitance, which may be compensated forby increasing the size of the drivers that drive their gates. Forexample, in the embodiment of FIG. 3, driver 306 is sized larger forhigh-V_(T) nMOSFETs 308.

[0019] Another embodiment utilizing high-V_(T) nMOSFETs and larger sizeddrivers for an on-chip register file is shown in FIG. 4, where forsimplicity only one memory cell 402 and one word line 404 are explicitlyillustrated. Also shown in FIG. 4 is driver 406 for driving word line404. Pass nMOSFET 408 is a high-V_(T) nMOSFET, and is sized larger toachieve the desired performance. Again, similar to the description ofthe embodiment of FIG. 3, pass nMOSFET 408 is a high threshold voltagetransistor in the sense that its threshold voltage is higher (e.g., 80mV to 300 mV) than the threshold voltage of other, lower thresholdvoltage transistors, such as transistors in memory cell 402, or is suchthat its leakage current is substantially less, e.g., ten to one hundredtimes less, than the leakage current through other, lower thresholdvoltage transistors, such as transistors in memory cell 402. Driver 406is sized larger in order to compensate for the increased gatecapacitance of pass nMOSFET 408.

[0020] For other embodiments, a negative voltage with respect to ground(substrate) is applied to the gate terminals of access or pass nMOSFETsnot performing a read operation. The application of a negative voltagein this manner may significantly reduce leakage current. For example, inFIG. 5, voltage generator provides a negative voltage to the gates ofaccess nMOSFETs 504 when cell 506 is not being read. Voltage generatormay be coupled to a memory controller, not shown, or to driver 508 so asto provide a negative voltage when cell 506 is not being read, and toprovide an open circuit (very high impedance) to word line 510 when aread operation is being performed. Voltage generator 502 may be combinedwith driver 508 into a single functional unit.

[0021] The voltage transition of word line 510 when transitioning from aread operation to a no-read operation is illustrated in FIG. 6. When ina read operation, the voltage of word line 510 is at V_(cc), whereaswhen transitioning from a read operation to a no-read operation, thevoltage transitions from V_(cc) to negative voltage V_(nx), asillustrated in FIG. 6. It should be appreciated that FIG. 6 is forillustrative purposes only, and the actual shape of the voltage curvemay be different.

[0022] The use of a negative gate voltage during a no-read operation maylead to higher electric fields over the gate oxide of an access or passnMOSFET than for the case in which a ground potential is applied to thegate terminals. To help mitigate possible reliability issues due tothese higher electric fields, some embodiments may employ thicker gateoxides for the pass or access nMOSFETs than that used for other nMOSFETsor processes.

[0023] Another embodiment employing negative gate voltages for a cell inan on-chip register file is shown in FIG. 7, where voltage generator 702provides a negative voltage to the gate of pass nMOSFET 704 during anon-read operation.

[0024] For other embodiments, use is made of the observation thatleakage current through two equally sized nMOSFETs in a stackconfiguration is significantly less than leakage current through onlyone nMOSFET not in a stack configuration. Two embodiments making use ofthis stack effect are shown in FIGS. 8 and 9. In FIG. 8, one cell of anon-chip SRAM or cache is shown. Access nMOSFETs 802 and 804 are in astack configuration, connected together serially with the source of onenMOSFET connected to the drain of the other nMOSFET. (Which particularterminal of a MOSFET is the source or drain depends upon the directionof conduction current through the MOSFET.) During a read operation, thestack comprising nMOSFETs 802 and 804 couple memory cell 806 tocomplementary bit-line 808. Similarly, nMOSFETs 810 and 812 are in astack configuration, coupling memory cell 806 to bit-line 814 during aread operation.

[0025]FIG. 9 shows one memory cell of an on-chip register file. PassnMOSFETs 902 and 904 are in a stack configuration, so as to couplebit-line 906 to the drain of nMOSFET 908 during a read operation.

[0026] Stacking nMOSFETs reduces their effective gain. This reductionmay be mitigated by increasing the width-to-length ratio of thenMOSFETs.

[0027] Described herein are specific embodiments of the presentinvention. However, many other embodiments may be realized withoutdeparting from the scope of the invention as claimed below.

What is claimed is:
 1. A memory comprising: a memory cell; a word line;a first access nMOSFET having a gate connected to the word line; asecond access nMOSFET having a gate connected to the word line, whereinthe first and second access nMOSFETs are connected to each other in astack configuration and are connected to the memory cell.
 2. The memoryas set forth in claim 1, further comprising: a first bit-line connectedto the first and second access nMOSFETs; a third access nMOSFET having agate connected to the word line; a fourth access nMOSFET having a gateconnected to the word line, wherein the third and fourth access nMOSFETsare connected to each other in a stack configuration and are connectedto the memory cell; and a second bit-line complementary to the firstbit-line and connected to the third and fourth access nMOSFETs.